Can the sub-folders in a DS-5 project check out from different CVS repositories?
Hi All, My team is using ARM DS-5 Professional Edition (v5.19), and we are using build-in CVS function to control the source versions. We are having a problem of checking out folders from different...
View ArticleError simulation or Code ?
hi i have a problem simulating my code however i can't find the problem always @(posedge HCLK or negedge HRESETn) begin if(!HRESETn) begin counterA <= 16'b0; counterB <= 4'b0; counterC...
View ArticleRe: What is the advantage of floating point of CM7 versus CM4
I can't spend any more time on this. I haven't received any feedback. I always like to help the next person, so here's my full report out of discoveries and conclusions. I would still very much like...
View ArticleRe: armv5TE
Architecturally you need to include barriers where ever the architecture says you need to include barriers; anything else is making assumptions about the CPU micro-architecture which may work on some...
View ArticleRe: OPTEE 2.0 tee-supplicant issue
Hi Simon, It's been a while since Iast did this so some of this may be outdated, but please find my notes below for running the OP-TEE Hello World example TA found in this GitHub repository,...
View Articlearmlink tool consult
hi all. I want to recude the build image. but i find some functions are not used in my project. for example, two functions who comes from one source file. now fun1() is used, fun2() not used, they are...
View ArticleRe: armv5TE
Hi, Thanks for your attention, I wonder if I need to implement barriers(I have total freeze problems), I wonder this becauseit is written that ARMv5TE does not have instruction optimization. I am...
View ArticleRe: Use of *ID signals in multi master design.
Hi yasuhikokoumoto, I'm using AXI4. Actually it seems that Xilinx's interconnect follows the recommendations from AXI specification A5.3.5 (Interconnect use of transaction identifiers). This means...
View ArticleRe: How to know thumb code or arm code?
This may be a bit late but other users might be interested in the info. I will list the steps that are needed to decode an ELF file in general (there may be some specific based on the processor...
View ArticleRe: when and where will the LDP instruction trigger an exception ?
Hi Harris, Thank you for reply. This code runs before the MMU is enabled. According to your suggestion, I move it after the MMU is enabled, It runs well.
View ArticleRe: when and where will the LDP instruction trigger an exception ?
Hi Daith, Thanks for your replay. SCTLR_EL1.A , SCTLR_EL2.A, and SCTLR_EL3.A are disabled. The code runs on EL3 in the DRAM.
View ArticleIs anyone working on Mali-T62x for Linux 4.9?
http://malideveloper.arm.com/resources/drivers/open-source-mali-midgard-gpu-kernel-drivers/ Works on 4.8 but 4.9 expects ‘struct vm_area_struct **’ instead of ‘struct page **’ etc.
View ArticleRe: Cortex-A8 - accessing banked registers from monitor mode
peterharris: Hi Peter,When we are trying to change the mode from Secure_Supervisor to NON_Secure_Supervisor, we go to Secure_monitor by invoking "SMC #0". As part of the Secure_monitor handler when...
View ArticleHi all,
When we are trying to change the mode from Secure_Supervisor to NON_Secure_Supervisor, we go to Secure_monitor by invoking "SMC #0". As part of the Secure_monitor handler when we try to write SCR...
View ArticleHow to add records into Firebase in iOS sdk?
Hello friends, As an iOS developer, I faced a lot of queries during development, I have searched many social networking sites and joined groups to resolve my issue, and finally I found an iOS developer...
View Article翘首以盼的 Bluetooth 5 终于到来！
祝贺 Bluetooth SIG！今天他们宣布正式采用 Bluetooth 5 规范！这意味着 Bluetooth SIG 已向公众公布该规范，为成员公司开启了 Bluetooth 5 产品商用化的大门。虽说今天才成为官方规范，但 ARM 的 Bluetooth 5 技术开发和测试工作已进行了一年多时间。实际上，早在 2015 年 8 月，我们的实验室中就已诞生具备 2Mbps
View ArticleRe: Use of *ID signals in multi master design.
Hi yasuhikokoumoto, thanks for the answer. I suspected that. What I don't understand is the fact that in most of the cases the system works properly. My guess is that the Xilinx AXI interconnect...
View ArticleRe: Use of *ID signals in multi master design.
Hi flyinged , I am afraid that the two masters have the same IDs. Xilinx AXI interconnect would generate response IDs for a slave which has not any ID. I guess the interconnect cannot distinguish the...
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