Hi All,
Requirement:
Globally Enable L2 and L1(Dside) Prefetch option
I need to confirm that setting L1 prefetch enable in L2 (Pl310 ) ACTLR needs to be done individually for all available arm cores on the system
MRC p15, 0,<Rd>, c1, c0, 1; Read ACTLR
MCR p15, 0,<Rd>, c1, c0, 1; Write ACTLR