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Re: Typical L1 and L2 access latency for SoCs made of ARM Cortex-A9

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Hi,

 

I'm afraid this is a question which does not have an easy or definitive answer!

 

Because of the unique way in which ARM-based SoCs are put together, all behave slightly differently. The latency of things like cache transactions and snoop transactions does not just depends on the IP which ARM supplies but also depends heavily on the particular cache implementation and bus fabric used in any particular SoC. These, and other things like them, are not part of the IP which ARM supplies to its licensees. They are free, for instance, to use third-party memory IP to build caches and also to use any other standard or proprietary bus fabric to connect together external components.

 

So, to find specific details of the timing and performance of specific parts, you would need to refer to the manufacturer's documentation. For the Exynos parts, you would need to look to Samsung.

 

Hope this helps.

Chris


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