Hi Anshul,
Could you please explain following line little better :
It is also worth noting that in many markets needing realtime response, TCM is generally available as a synthesis option in the Cortex-R family, so even in those markets there are better alternatives to cache lockdown ...
A TCM (Tightly Coupled Memory) is a flat memory which exists at the same (or similar) level in the memory hierarchy as the L1 cache, often split in to pairs so you have an I-TCM and a D-TCM. The processor can use TCM directly without needing to go via the cache for the TCM mapped address ranges.
Also could you please let me know the steps to perform cache lock down for any piece of code (I want to try it own my own).
As Wangyong mentioned, it isn't supported at all on the Cortex-A7. It is "optional" in the ARM architecture and "implementation option" in the standalone L2 cache controllers. It is very rarely actually implemented, because it is so rarely useful, so there is a good chance that you can't actually do this on your device.
HTH,
Pete
