We know that a Cortex-M0 or any other Cortex-M may have fewer interruptions implemented the architecture defined in the standard, so we can not use interrupts implemented as software interrupts by manipulating the registers SETENA / ClrEnable and SetPend / ClrPend.
For example, being the interrupt # 5 (Exception # 21) not implemented at the hardware level, this could be used as an interrupt / exception of software?
