Hi Gunther,
There are two issues here:
1) The AHB component always buffer a transfer - this is part of the problem. It means if the downstream bus slave return an error response, the bus master won't be able to see it. So this is not good. In some cases the bus components can make assumption that there won't be any error response coming from the bus slave, for example, if the bus component is an AHB to APB bridge for AMBA 2.0, where the APB protocol doesn't support error response, it is not a issue.
2) The bus bridge allows re-ordering of transfer from the AHB
Now this issue need to break down into memory types:
a) If the memory is Normal memory (ROM, RAM), and if the read back data is correct (if the read address is same as write address, it should return the new value in the buffer). Then the re-ordering of the transfer is not a issue.
b) If the memory is Device / strongly ordered, then the bus bridge should not re-order the transfers to the same bus slave. So it is a violation of the "memory ordering" model.
regards,
Joseph
