Re: Why A9 is multicore by A8 doesn't
Hi,I'd say... Hardware support for maintaining cache coherency (between the L1 data caches of the individual cores) is the main feature MPcores have, that earlier single core designs (like A8) lack....
View ArticleHow to define UEFI entry point when image is loaded in RAM by ARM trusted FW.
Hello I would like to have your help on Uefi boot on ArmV8 platform (aarch64).I’m trying to setup the entire boot on my platform based on Armv8 processors with Arm Trusted Firmware and UEFI (from...
View ArticleMOV opcode format ?
i got a simple question... Someone will tell me where does the limitation in the opcode Mov with access to the immediate value ? Is there a physically reason or is that only due of the CRSP type format...
View ArticleRe: How to define UEFI entry point when image is loaded in RAM by ARM trusted...
Bonjour nicolas, Peut être un début de réponse à ta question dans ce document :http://events.linuxfoundation.org/sites/events/files/slides/Korea%20Linux%20Forum%202013%20-%20UEFI%20and%20ARM.pd Peut-on...
View ArticleRe: How to define UEFI entry point when image is loaded in RAM by ARM trusted...
> Ou quelques réponses à la source Or some answers to the source https://wiki.linaro.org/ARM/UEFI
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Re: How to define UEFI entry point when image is loaded in RAM by ARM trusted...
Hi Jérome, Thanks for the information, unfortunatly the link between ARM Trusted FW and UEFI changed in the last monthes and I'm not sure the documenation you mentionned is up to date now. I'm not...
View ArticleRe: ARM v6 performance monitor: Can I record the instruction which caused the...
But this can only deal with instruction cache miss I guessWhy you think the approach will not work for data cache misses? It should work for any performance counter.
View ArticleRe: ARM v6 performance monitor: Can I record the instruction which caused the...
> 1. Which instructions are possible to cause a cache miss ? Many of the ARM11 cores support "hit under miss" so the data processing execution can keep progressing while a non-dependant cache miss...
View ArticleRe: arm v7 performance monitor:how to get L2 cache refill?
There are some hit and miss counters in the PL310 TRM (section 2.5.8 in the PDF, which I find easier to read than the online docs)....
View ArticleRe: ARM v6 performance monitor: Can I record the instruction which caused the...
Oh, I did not make myself clear. Basically, I want to rearrange our data structures to reduce the data cache miss ( and restructure the code to reduce the instruction miss). So I think I need to know...
View ArticleRe: Problems with interrupting LDM/STM Cortex M4?
I believe this could happen if you're in a multithreaded environment, and a context-switch is happening in the middle of the STM instruction. However, it would happen only if there is an error in the...
View ArticleRe: MOV opcode format ?
Martin Weidmann's answer is correct.Jérôme Décamps: I recommend reading the ARMv7 Architecture Reference Manual.On page 121, you will see the opcode and the different possibilities for the types of...
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Re: Problems with interrupting LDM/STM Cortex M4?
Hi paulgiangrossi, I'm sorry for late reply. Do you say that the re-start address of the STM was incorrect after returning an ISR? If it is true, It should be a problem. Could you change the Cortex-M4...
View ArticleRe: ARM v6 performance monitor: Can I record the instruction which caused the...
Hi chenzhanalbert, how about setting the FI bit of the system control register (CP15 register 1), if the mismatch came from the hit under miss feature. You can prohibit the hit under miss by setting FI...
View ArticleRe: MOV opcode format ?
Hi ackmicro-san, although I cannot understand well the purpose of your question, do you ask the reason why a 32-bit immediate move instruction to a register will be replaced for the pc relative load?...
View ArticleRe: MOV opcode format ?
In reality my question is not an answer to a programming problem . It was just a generic question about whether it could have a source of physical limitation.The answer provided just allows me to...
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