Re: data abort and prefetch abort
Some ARM7 cores ship with an MPU, which allows memory protection but not VA to PA translation. An MPU can generate faults (writes to a read-only region, for example), in the same way that an MMU can....
View Articlein gcc we use __attribute__((interrupt("FIQ"))) for fiq handler in C. what is...
in gcc we use __attribute__((interrupt("FIQ"))) for fiq handler in C. what is the equivalent using armcc compiler?
View ArticleRe: How can I use imx6 in Asymmetric (APM) mode?
Hello Marco, We have AMP support for the Cortex-A9. As Drew noted, care needs to be taken in memory and device usage. PolyCore Software has tools and runtime software for multicore applications,...
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Usage of Neon unit in coding other than SIMD operations?
Hi all experts, I just want to know the usage of neon unit in Cortex-A8/A9 in for applications other than SIMD operations??? Is there any perticular area (of coding) where we can use neon othere than...
View ArticleRe: Installing the ARM DS-5 setup in my windowsXP service pack3 dekstop....
First thing I would try is re-downloading the installer. It could just be that it got corrupted during download/decompression.
View ArticleRe: what is Tightly coupled memory? Is there any possible way to use it for...
Just adding to what George wrote... As you said you're working with Cortex-A8 and Cortex-A9, it's worth noting that none of the Cortex-A processors support TCM as an option. The closest equivalent...
View ArticleRe: Usage of Neon unit in coding other than SIMD operations?
You sometimes seen NEON instructions used for memcpy like operations, which I don't think is strictly SIMD.
View ArticleRe: Starting to work in REALVIEW PLATFORM BASEBOARD FOR ARM1176JZF-S (...
Do you have a DStream or RVI unit? You'll need one to connect the DS-5 debugger to the board for baremetal debug and image load. Assuming you do... DS-5 has platform support for the PB1176. So you...
View ArticleStarting to work in REALVIEW PLATFORM BASEBOARD FOR ARM1176JZF-S ( SOFTWARE...
I AM WORKING FIRST TIME IN ARM BOARDS. PLEASE GIVE ME THE STEPS OF RUNNING A C PROGRAM IN ARM1176JZF-S WITH ARM DS-5 TOOLS( THE LICENSE OF WHICH I HAVE AND WHICH IS ALREADY INSTALLED IN MY PC ) .I HAVE...
View ArticleRe: Usage of Neon unit in coding other than SIMD operations?
and you can use http://projectne10.github.io/Ne10/ to speed up your development.
View ArticleA question about using IRQ of DMA with RTE uVisoin v5.
Hi, experts. I'm recently working on CMSIS RTOS with MDK-ARM V5.1, on STM32F103 MCU. I'd like to know about using IRQ of DMA on RTE(Run Time Environment). My application uses following functions.-...
View ArticleHow to wait for multiple threads on CMSIS-RTOS API
Hi, experts. I'm recently working on CMSIS-RTOS API with MDK-ARM V5.1, on STM32F103 MCU. I'd like to know how to wait for multiple threads.(and mode)andI'd like to know how to wait for any one of...
View ArticleEmbedded Web Server(EWS)
HI experts,I am vikram,I am new to this field,I am trying to do the Embedded Web Serer by using the LPC1768.I am try to write the code my own but i cant my collies told me try for sample code for that,...
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Re: Starting to work in REALVIEW PLATFORM BASEBOARD FOR ARM1176JZF-S (...
Thank you sir. But sir how do I know whether I have DStream or RVI? I am following the procedure you have mentioned but what to fill in the connection of the debug configuration( when I press browse...
View ArticleRe: Configure Cache size of Cortex A9
No, it is a synthesize option, hardware feature. The software has no control of it.
View ArticleRe: Configure Cache size of Cortex A9
OK, so during implementation means, the implementation of the HW? So, when buying one, I must choose my options?
View ArticleRe: Configure Cache size of Cortex A9
Sort of. But it is not like shopping for a desktop, which you can choose how many memory to have. It is a CPU, different manufactures have different implementation. Have a look at the specification...
View ArticleCan I select my own cache replacement policy?
I am using the Cortex A9, according to the document: "Cache replacement policy is either pseudo round-robin or pseudo random."Is there any info, on exactly what these mean? Is the policy set only by...
View ArticleRe: Can I select my own cache replacement policy?
It's controlled via the SCTLR.RR bit: Cortex-A9 Technical Reference Manual: 4.3.9. System Control Register However, this bit can only be modified when in the Secure state. On some development boards...
View ArticleRe: How to wait for multiple threads on CMSIS-RTOS API
Hello Tino, did you have a look at the example projects that are part of MDK v5? Usually, the RTOS-Blinky project comes with four threads that are simulating a stepper motor driver. Please check this...
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