LDP/STP burst transaction question in ARMv8
hi, experts:In ARMv8 arch：LDM/STM has been replaced by LDP/STP instructionUser could use LDP/STP to produce some continual burst memory transactions.Take CA57 as an example:CA57's DCache line =...
View ArticleCortex-A7 dual-core cache SMP operation
HiI have a question of Cortex-A7 dual-core cache.In Cortex-A7 MP trm, SMP bit in "Auxiliary Control Register" must be set before any type of cache operation.Now my program uses just one core, so:Core0...
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New "ST MCU Finder" for Android
“ST MCU Finder” free app is the best way to find the right STM32 & STM8 MCU among a selection of more than 400 references.Share your results and instantly access to key technical features and...
View ArticleARM tools use GCC compiled library
HiI'm using ARM tools (RVDS4) to develop a project. Now I want to use a software lib which compiled by GCC.I read spec of GCC and add a compile flag "-mabi=aapcs" to GCC and rebuild the...
View ArticleHelp me Start whit ARM!!! (xperianced other langugaes) more questions before
hi, im coming from AVR i read C++ java android AVR python and.... but (C++ im better at it then others:D but just know others and can make programs:P, frist language i learned!) also sorry my...
View ArticleRe: Help me Start whit ARM!!! (xperianced other langugaes) more questions before
i just relized how retarded i wrote this ! sorry !!!!! im was so confused sad and angry:D happens when i dont understand something
View ArticleRe: Getting Mali Graphics Debugger to work - "unable to read stream"
Hello again, I've finally rooted my Nexus 5 and configured the necessary files for the mgddaemon on the phone, but I really don't know how to rename or link the necessary libraries. The Mali Graphics...
View ArticlePossible error in Mali Graphics Debugger v1.2.1 User Guide
I'm writing this post because I thing there is an error in page 10 of the Mali Graphics Debugger v1.2.1 User Guide. When restoring the old egl.conf file it says: cp /system/lib/egl/egl.cfg.bak...
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Re: Help me Start whit ARM!!! (xperianced other langugaes) more questions before
ARM means a processing core, there are loads of different chips with different peripherals on them. The ARM core is 32 bit rather than 8-bit. The instruction set is pretty much compatible except there...
View ArticleRe: Does ARMv8 SOC support cache lockdown?
The ARM Cortex-A57 does not support locking of the L1 or L2 cache, see these pages of the Technical Reference Manual: ARM Cortex-A57 MPCore Processor Technical Reference Manual: 6.1. About the L1...
View ArticleRe: EBFE is to x86 as ____ is to ARM64
The A64 branch to self syntax would be (with ARM's tools): B . That is the branch instruction (B) followed by a dot (.). Would assemble to 0x1400_0000 (from section C4.2.6 of the architecture...
View ArticleRe: What is pipeline shutdown in ARM ? How this is achieved ? Does it plays...
I'm afraid that I don't recognize the term "pipeline shutdown", did you see it in one of ARM's technical reference manuals? ARM processors do support a "shutdown" power mode. Is that what you meant?
View ArticleRe: What is pipeline shutdown in ARM ? How this is achieved ? Does it plays...
Yeah I got the reference from this dochttp://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf It states fine grained pipeline shutdown.Need more info on this
View ArticleRe: LDP/STP burst transaction question in ARMv8
It _probably_ would trigger a series of bursts, but probably not for the reason that you think. First thing to say is the architecture does not generally define exactly what kind of bus accesses a...
View Articlehow to set breakpoint by accessing co processor registers in ARM from...
The break point can be set and enable/disabled using the Jtag debugger. In this case how to access the internal registers in the ARM co processor to set the breakpoint in the address during run-time
View ArticleRe: performance difference of long descriptor vs short descriptor page table...
I don't see a problem with your terminology I have (personally) never measured the performance, so can't quote figures. But a couple of observations... Assuming you are talking about ARMv7-A, then...
View Articlequestion about CONTEXTIDR_EL1 and ASID field.
hi, experts:I am studying ARMv8 manual.CONTEXTIDR_EL1 and TTBR0_EL1(including ASID field)are part of the virtual memory control registers functional group.So, is there any sample descrbing how to use...
View ArticleRe: Getting Mali Graphics Debugger to work - "unable to read stream"
Hi draquod, I should mention that there are debugging tools available for Adreno here: Mobile Gaming & Graphics - Adreno Tools and Resources - Qualcomm Developer Network. These are designed for...
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Re: What is pipeline shutdown in ARM ? How this is achieved ? Does it plays...
I would assume that this is some advanced form of clock-gating - the design detects when the pipeline is not needed, and stops clocking it if it is not needed. This removes the dynamic power element of...
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