Re: Android question - how to connect Nexus 7 through I2C
Thanks, we have updated the wiki documentation with this information.
View ArticleClik here to view.
Re: How to change my solution to run on multicore processor like Cortex - A9?
Hi sir,Hope the following introduction will help you. We have both Freesclale and TI board. We are a professional ARM board Manufacturer and cooperated with TI, Freescale, ATMEL and other popular...
View ArticleHow to use the free rtos in lpc1768...?
How to use the free rtos in lpc1768...?Where i can get the sample code for this controller by using the free rtos...? RegardsVIKRAM
View ArticleHow to get CPU cycles of a function using DS5 (or Streamline)?
Hello, I'm trying to optimize some functions in ARM Cortex A9 architecture. Now, I want to judge whether the optimization is valid by reading and comparing the executed CPU cycles. But I can't find...
View ArticleOmap5432-uEvm Best SDK choice
I'm searching the good way, for the best kernel compilation of the Omap5432-uEvm.Which is the best SDK for this plateform ? Ubuntu/PanDa/ANdroiD ? I mean Ubuntu stay the most Open to my case. But I...
View ArticleRe: How to get CPU cycles of a function using DS5 (or Streamline)?
By default DS-5 is a time-based profile - so it takes samples over the program counter every 1ms, and over a period of many samples it can build up a statistical picture of what the program is doing,...
View ArticleRe: Raspberry pi with streamline ds-5
Hi, It seems Streamline cannot communicate with the gator daemon running on your target. Please check that gator daemon is running in the background, by using the 'ps' command. If you are connected to...
View ArticleRe: C9912E: No --CPU selected
This probably means that you need to set the CPU correctly for the compiler. To do this, right-click on your project in the Project Explorer view and select Properties. In the Properties dialog,...
View ArticleHow Can We Empower Machines to Understand? (Find Out on May 29th in Santa...
I'm enthusiastic about the potential of "embedded vision" – the widespread, practical use of computer vision in embedded systems, mobile devices, PCs, and the cloud. Processors and sensors with...
View ArticleWhy is the I-cache designed as VIPT, while the D-cache as PIPT?
Hi, In Cortex-A8's architecture, I'm trying to understand why the I-cache is chosen to be in VIPT form (Virtually Indexed Physically Tagged), while the D-cache is PIPT (Physically Indexed Physically...
View ArticleClik here to view.
Why is D-cache as PIPT, while I-cache VIPT in A8?
Hi, In Cortex-A8's architecture, I'm trying to understand why the I-cache is chosen to be in VIPT form (Virtually Indexed Physically Tagged), while the D-cache is PIPT (Physically Indexed Physically...
View ArticleRe: Code for integer division on Cortex-A8?
daith wrote: It's worth remembering too that division by a constant can be done much more efficiently. Although not often applicable, it is also interesting to note that exact division (i.e. where it...
View ArticleRe: Code for integer division on Cortex-A8?
The original and best paper on all this isDivision by Invariant Integers using Multiplicationby Torbjorn Granlund and Peter L. Montgomerysee alsoImproved division by invariant integers
View ArticleRe: Code for integer division on Cortex-A8?
If you're really desperate here's a routine which does unsigned division by a constant.d not equal to zeroInitialise dr and sh such thatShift d left while zero to give dbig with top bit set and shwzcnt...
View ArticleRe: How to get CPU cycles of a function using DS5 (or Streamline)?
Thanks. Very detailed and clear.So, as you mentioned, DS-5 can't provide CPU cylces counter, could you konw any other ARM tools which can provide this function?
View Articlemonitor debug-mode vs halting debug-mode in ARMv7 core
hi,experts:ARMv7 ARM.pdf的C1.2.1 Invasive debug chapter提到了2种debug-mode:1. Monitor debug-mode2. Halting debug-mode 不清楚哪种情况下使用"Monitor debug-mode".似乎目前的JTAG tool：都是使用Halting debug-mode best wishes,
View ArticleRe: Error: C9932E: Cannot obtain license for Compiler (feature compiler5)...
hello Sam Ellis, Thanking you for your response, 1. Is there any specific way to select the toolchain , i mean how do i select the Altera SoC EDS include a bare-metal gcc toolchain. 2. actually i am...
View ArticleClik here to view.
I don't understand cache miss count between cachegrind vs. streamline
I am studying about cache effect using a simple micro-benchmark. I think that if N is bigger than cache size, then cache have a miss operation every first reading cache line. (Show 1.)In my...
View ArticleAMBA 5 CHI Specifications
Hi,Can I get reference document for AMBA 5 CHI specification.? Please Can anyone share me that doc...? Thanks & Regards,Rakesh Reddy.B
View Article
