Quantcast
Channel: ARM Connected Community: Message List
Viewing all 8551 articles
Browse latest View live

Re: Are simultaneous accesses to both ITCM and DTCM of Cortex-M7 possible?

$
0
0

Hi all.

 

I have misunderstood Cortex-R specifications. In the Cortex-R5 case, it has the same arbitration scheme as Cortex-M7. Therefore Cortex-R and Cortex-M7 cannot make concurrent accesses to both ITCM and DTCM. To the contrary, the legacy ARM (such as ARM9 or ARM11) could make concurrent accesses to both ITCM and DTCM, I think. It is why the paths from PFU to ITCM and from LSU to DTCM are individual.

 

Best regards,
Yasuhiko Koumoto.


Re: C Programming and pointer sizes on ARM processors.

$
0
0

As for the latter part of your comments, I understand well and agree you. As for the former part, I cannot find significance. I think the understanding for the typecast is different from you. You seems to think it is a method of not causing warnings. I believe it is the only method of data conversion. I think we need not to care the pointer size. By the way, why do you mention the pointers in the structure?

Re: C Programming and pointer sizes on ARM processors.

$
0
0

There are parts of my reply that are not always valid, and parts of your reply, which also are valid in some cases. Why I mention the structure, is because it's likely that aps would store a pointer to something as a structure member or directly in memory.

I've used structures to hold some data, which could be of different types myself.

 

Personally, I avoid typecasting if possible.

Here's my solution to a problem where I need to supply a pointer to memory, but I do not know what datatype it actually points to; it can be one of 3 types:

 

typedef struct GDevice GDevice;

struct GDevice

{

   GDevice *next;

   union{

       void *address;

       uint32_t *address32;

       uint16_t *address16;

       uint8_t  *address8;

   };

};

 

Now the above is not critical code, and all pointers are of the same size. But I do not have to typecast at all. When I set the address, I write to 'address'. When I need the 32-bit pointer, I read address32. When I need the 16-bit pointer, I read address16.

I can do this, because I know the memory location will always be divisible by 4.

If I had to typecast, my code would look very messy (I actually cleaned up typecasting this way; it can make a huge difference in how your code look).

Another advantage is that you do not have to go through every reference in case you one day need to change a uint16_t to a pixel16_t. You don't need to fix up all the type-casts. (Yes, in the particular code, I use pixel8_t, pixel16_t and pixel32_t now, plus a pixel_t of course).

Re: #HappyNewYear !

$
0
0

あけましておめでとうございます

Re: C Programming and pointer sizes on ARM processors.

$
0
0

Thank you for detailed explanations. I understand your style and it may be useful. I might sometimes use your coding style in the future.

Re: #HappyNewYear !

cM4 setup vector table for external interrupts

$
0
0

I don't want to setup the vector table for all my external interrupts. For instance I only need the timer4 IRQhandler at IRQn 30. How can I make an offset in the table? Is this necessary?

CMSIS for TI Cortex-M4 LaunchPad

$
0
0

In a few weeks I'll be teaching an introductory course in microcontrollers, and our lab exercises will be using the Texas Instruments TM4C123XL LaunchPad. I've created an Eclipse project template for C programs that uses CMSIS and the OpenOCD debugger, and I'd be happy to get suggestions for improving it. In particular, I would like feedback on the TM4C123GH6PM.h file that abstracts the peripheral devices in CMSIS style and on system_TM4C.c that initializes the clocks at reset. Everything can be downloaded from github. My intent is to make the development process as portable and inexpensive as possible, so I have intentionally avoided software tools that are not open source. Also, I am intentionally avoiding the use of TI's TivaWare because engineering programs in the U.S. are expected to emphasize standards-based design and CMSIS is the published standard for Cortex-M code development. I know that a professional software developer might make different choices, but this work is for teaching at the introductory level where I expect students to get their hands dirty and the programs are relatively small.


Re: Can the cortex m3 stream videos?

$
0
0

Wow, that's an impressive analysis, at least of the abstract capability of a wide range of Cortex-M3 chips.

 

Please allow me to offer a couple specific examples.  These are based on Cortex-M4 (Freescale Kinestis K20) running at 96 MHz.  Minimal use of the DSP extensions was made, so you could probably expect similar performance from Cortex-M3 at about 100 MHz, assuming similar buses and DMA capability.

 

First, here's a LED panel project I made several months ago, displaying 30 Hz video at low resolution (90x48 pixels) and streaming 44.1 kHz (mono) audio.

 

http://community.arm.com/groups/embedded/blog/2014/05/23/led-video-panel-at-maker-faire-2014

 

The video and audio data leverage the Kinetis eDMA engine.  The uncompressed data is read from a SD card, in SPI mode, using polling for the SPI peripheral.  Testing showed approx 50% CPU usage, mostly for the SPI data transfer.

 

 

A 320x240 SPI-interface display was mentioned.  This is another place I've done significant optimization work.  Here's a blog article, with a sample video:

 

http://www.dorkbotpdx.org/blog/paul/display_spi_optimization

 

As you can see in that article, simplistic software design for these displays results in slow performance, even with a fast CPU.

 

Above, a theoretical 32.5 Hz refresh rate was mentioned, based on the assumption of 50 MHz SPI clock.  Since publishing that article, I've talked with others attempting similar optimization.  Testing has shown many of those displays do not work reliably with 42 MHz clock speed.  Reliable specs are hard to find, but some datasheets spec a maximum SPI clock of only 10 MHz.  I have personally done a LOT of testing with 24 MHz SPI clock, but always while running the display at 3.3V (well above its minimum 2.2 or 2.4V), with good results.

 

 

If your video is compressed with any DCT-based algorithm, odds are slim a Cortex-M3 will be capable of decoding the data in real time at any significant resolution.  Even just moving the bytes from a SPI port to RAM can take a lot of CPU time if DMA is not leveraged efficiently.

 

 

Cortex-M7, when chips appear in the 350 to 400 MHz range, might open up more possibilities.  Maybe?  As you can see, I actually do quite a bit of work on optimizing open source middleware.  If anyone from ARM actually reads this message, please let me know when an updated v7m architecture reference manual is published?

Re: Can the cortex m3 stream videos?

$
0
0

Paul Stoffregen - Great to hear about other Cortex-M options! -Thank you for chipping in (eh, that was lame, wasn't it?)

Yes, I made a lot of assumptions in my answer above; that's true. I've personally used the 50MHz clock with my SPI display, which is a low-cost display module from China (you probably know already). -I must say that your library is definitely impressive. Note: I just cloned the sources and viewed them lightly. I think you may be able to improve on the character-output by drawing the characters vertically instead of horizontally - I did this in my own code.

The reason I think this is the case, is that there are much more adjacent pixels vertically than horizontally (well in my font anyway). Saving are most of the time when you move the window without resizing it.

 

x-627 - I think I forgot to mention that there are 8-bit parallel and 16-bit parallel displays available as well. If pushing things to the limit, I believe it would be possible to get a data rate of 8 bits per clock cycle on a 16-bit parallel display or 4 bits per clock cycle on an 8-bit parallel display, however, the display would most likely not be able to handle a clock rate that high. I'm not currently able to test this theory, but this particular setup will most likely require the SCT found in the LPC43xx or LPC541xx.

Re: cM4 setup vector table for external interrupts

$
0
0

Hi jvanmont,

 

I'm not sure that the timer4 interrupt is assigned to IRQ30. What is your device? Anyway, if you would like to know the vector offset of IRQ30 of Cortex-M4, it is 0x000000B8. You should at least put the timer4 IRQhandler address into 0x000000B8.

 

Best regards,

Yasuhiko Koumoto.

Re: cM4 setup vector table for external interrupts

$
0
0

yasuhikokoumoto Hi, my device is STM32F429. I think I can assign it in my startup.s but I'm not sure how to assign the address to tim4 IRQHandler.

Re: Re: cM4 setup vector table for external interrupts

$
0
0

Hi jvanmont,

 

I checked the STM32F42xx Reference Manual (http://www.st.com/st-web-ui/static/active/jp/resource/technical/document/reference_manual/DM00031020.pdf) and confirmed the timer4 interrupt is assigned to IRQ30. Do you want to know how to write the original startup.s? If it is so, please refer to the post "Writing your own startup code for Cortex-M" (http://community.arm.com/docs/DOC-8769). I extracted the essential part from the post and added the new vector entry of the timer4 handler.

 

----[snip]-----

.align  2

.long  _stack/* 0x00000000 The initial stack pointer (defined by the linker-script) */

.long  Reset_Handler   /* 0x00000004 */

.long  NMI_Handler   /* 0x00000008 */

.long  HardFault_Handler/* 0x0000000c */

.long  MemManage_Handler/* 0x00000010 */

.long  BusFault_Handler /* 0x00000014 */

.long  UsageFault_Handler/* 0x00000018 */

.long  0     /* 0x0000001c */

.long  0     /* 0x00000020 */

.long  0     /* 0x00000024 */

.long  0     /* 0x00000028 */

.long  SVC_Handler   /* 0x0000002c */

.long  DebugMon_Handler /* 0x00000030 */

.long  0     /* 0x00000034 */

.long  PendSV_Handler   /* 0x00000038 */

.long  SysTick_Handler  /* 0x0000003c */

/*  .long      ..._IRQHandler */

/* 0x00000040 and forward. IRQ vectors specific to your microcontroller follows here... */

.align 7 /* 0x00000080 */

.space 0x38 /* 0x000000B8 */

.long tim4_IRQHandler

  .text  /* Put everything in the text-section from now on... */

  .align  /* Make sure address is aligned for code output */

----[snip]-----

 

Best regards,

Yasuhiko Koumoto.

Re: cM4 setup vector table for external interrupts

How to fix "*** [obj/flash_board_cstartup.o] Error 2"

$
0
0

Hello,

I am new to ARM. Right I am trying to get up to speed with the SAM7S examples pack "at91sam7s-ek" available from the Atmel website.

When I load any project into Eclipse I get the following error After building project.

 

make: *** [obj/flash_board_cstartup.o] Error 2

 

I have checked that paths are correct and that the files are where they are supposed to be.

Is there anyone that can help me to get this running or can anyone recommend a better set of examples that actually work for the SAM7S devices.


Re: cM4 setup vector table for external interrupts

$
0
0

Hi jvanmont,

 

there are two ways to specify the 'align parameter'. One is to specify a direct byte boundary and another is to specify a boundary by the power of two. GCC (GNU-assembler) adopts the latter way. Regarding ALIGN 7, please refer to the jensbauer's explanations.


Best regards,
Yasuhiko Koumoto.

Re: Trouble creating a poll

$
0
0

Hi Brad, Thanks for following up. I have tried Ben’s suggestion to post the poll to a community group many times.  Just to make sure it wasn’t a problem with a link to any particular group, I tried two different groups, IoT and embedded.  Neither time could I complete the poll.  I keep getting the same error message saying I might be logged out (I am not) and that I should see my system administrator.  But I do not know who that is.

 

My poll content is saved.  Perhaps that is the problem and I need to start all over again?  Any suggestions that you can think of would be greatly appreciated.

 

Thank you,

Marni Welch

Getting a link to an ARM documentation page or pdf

$
0
0

Unfortunately it isn't as obvious as it should be how to get a link to a page in the ARM documentation.

 

If one starts at

 

ARM Information Center

 

and then follows the contents list down clicking on entries the link at the top of the page does not change, and there is no nice chain icon to give a link to the selected page like one gets with Google maps.

 

The trick is to get the link in the contents entry for the page on the left hand side.


On Windows using Google Chrome right click on the contents entry and press 'Copy link address' then click CTRL+V in the message one is writing or editing, then one will get a nice line describing the page in the document like the following


Cortex-M0+ Technical Reference Manual: 3.5. Processor core registers summary

 

For Internet Explorer the right click menu selection is 'Copy shortcut'

For Firefox it is 'Copy link location'. So not a lot of commonality in the name!

 

I think the ARM Information Center pages would be improved by having a link icon to make this more obvious. Also using American in the title when it is based in England is strange but then I suppose the UK isn't the main target

 

To link to a particular page of a pdf document one puts for instance #page=5 at the end of the pdf link, e.g. here is a link to the block diagram on page 9 of the ARM710T pdf

There's no automatic prettifying here but one can always type over ones own text without affecting the link

 

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0086b/DDI0086B_710t_ds.pdf#page=9

 

A problem I've found is with top level contents pages, for instance under


ARM DS-5

 

You'll find the shortcut for shortcut for all the versions e.g. Version 5.0 come out exactly the same, and even worse the pages for the top level for

ARM DS-5 Debugger  and

ARM DS-5  Streamline

are exactly the same too so you have to get a specific lower level page for instance one with the pdf icon at the top instead

Re: hi i am trying to understand arm neon instruction

$
0
0

Negative minimums are more interesting as they have a larger absolute value. In "real maths" the two minimums will give:

 

  • -32768 * -32768 * 2 = 2147483648

 

In binary 2's complement this is 0x80000000, so if you don't saturate then the actual signed result effectively inverts the real answer to minus 2147483648 which is very very wrong =) With saturation you will get a positive 0x7FFFFFFF (2147483647) [of which you only keep the high half, so 0x7FFF ends up in registers].

 

HTH,
Pete

Memory allocation for Cortex-M4

$
0
0

I know Cortex-M4 doesn't support virtual memory. Do you always have to load VA from some LA in flash? For instance you allocate empty value memory at compile time.

Viewing all 8551 articles
Browse latest View live