It looks that you are already having two vector tables as well. In that case, you change the VTOR and perform a reset. I am not sure if this is the correct way.
By the way, what is really the need of having 2 images?
Joseph Yiu's book Definitive guide to Cortex M3, M4 gives some similar examples (Chapter 7, section 7.5)
Which MCU it is?
Do you already the chip or would you like one?
Note: r6 should be 0, not 1.
It's only necessary to set bit 0 in PC, that is if you're changing PC directly.
So you should load the SP from address 0x00000000 and PC from address 0x00000004.
Bit 0 is already set for all handlers in the vector table, so you do not need to change anything.
ARM recommends using BX to load PC:
movs r0,#0
ldr r1,=SC
str r0,[r1,#VTOR]
ldr sp,[r0]
ldr r1,[r0,#4]
bx r1
... but if you need the code to be shorter, I believe the following will work ...
movs r0,#0
ldr r1,=SC
str r0,[r1,#VTOR]
ldmia r0!,{sp,pc}
Gopal Amlekar: It can be useful having two images, where image#1 may update image#2 (for firmware update purposes). If image#2 is not present, image#1 could be either waiting for firmware or execute a 'default' or 'bare minimum' firmware.
Normally image#1 would execute image#2 almost immediately (right after verifying that it actually makes sense and is a valid image).
Jacob Beningo wrote an excellent document on the bootloader subject called Bootloader Design for MCU's in Embedded Systems.
You may also be interested in Does anyone know how I can remotely update code to distant arm system?
Jérôme Décamps: Click LIKE, click LIKE...
Thanks jensbauer, So it is similar to bootloader app I guessed. Some MCUs have inbuilt bootloader, isn't it? I think STM32F4 has one.
Also in this particular case, if VTOR is updated in the image #1, then it would later always execute image #2 when power cycled. It won't be able to get back to image #1 unless VTOR is again changed to vector table of image #1.
Changing VTOR isn't permanent; it's just like any other hardware register, and has a default on startup.
-So power-cycling will always execute image#1 in this particular case.
Most microcontrollers have a boot-ROM, yes. This makes it possible to program the devices in other ways than JTAG and SWD, for instance via UART or USB, but this of course depends on the boot-ROM code.
Thanks. I had this misunderstanding of VTOR..
Hi,
I have few basic questions for Mali packages.
Please understand my lack of understand in this field.
My company designed a new board in purpose of playing HD videos on Linux DirectFB envionment.
And the video player would may be VLC player.
In my case which packages are required for the best graphic performance?
OpenGL ES can enhance the graphic performance?
Does it because fbdev uses 3D APIs?
If 3D APIs are not required, can I replace OpenGL ES with OpenCL?
Additionally do I need to port OpenCL to enable NEON? Or NEON can be utilized without OpenCL or OpenGL ES?
PLEASE please help me.
Project time schedule is quite desperating..
Thank you.
Hi, Jorg.
I submited my last question in this link.
Which Mali packages are required for the best graphic performance of video playing on Direct FB?
Please leave any idea if you can.
Thank you.
Nari
Hi Peter,
regarding the instruction cache, it is able to turn on without MMU, isn't it?
Best regards,
Yasuhiko Koumoto.
Yes, I think so.
thanks!
Thank you for your reply, Chris.
You've been so much help to me!
Nari
According to the documentation, on Cortex-M0, the exception vector table is fixed at address 0x00000000.
However, since a vendor can customize the behaviour of virtually anything, I know of one implementation, which allows you to change it, though; perhaps there are more.
Fortunately, Cortex-M0+ has a VTOR.
Which device in particular are you writing code for ?
Cortex-M0, not Cortex-M0+.
Dear all,
I am sharing below two links for good tutorials on ARM GNU toolchain:
http://www.bravegnu.org/gnu-eprog/
http://www.state-machine.com/arm/Building_bare-metal_ARM_with_GNU.pdf
Please provide routes to any other document/tutorial that would add value to the above mentioned.
Nice one. Thanks for sharing.
Articles written by jensbauer in this community are also interesting which use the GNU assembler. Here are the links for ready reference:
Useful assembler directives and macros for the GNU assembler
Hi Jens,
Happy New Year!
Cortex-M7 Technical Reference Manual (TRM) is now online
ARM Cortex-M7 Processor Technical Reference Manual
regards,
Joseph
Hi Yasuhiko,
Depends on what you mean by simultaneous accesses, the following accesses can happen in parallel:
-PFU access to I-TCM
-LSU access to D0/1-TCM
In the TRM statement you quoted, please note the word "each":
Each TCM interface receives requests from the LSU, PFU, and AHBS.
So I-TCM has an arbiter that deal with multiple accesses, and same for D0/1-TCM which has a separated arbiter.
What you cannot do is
- PFU (instruction fetch) and LSU (data accesses) both access to I-TCM in the same cycle, or
- PFU and LSU both access to D0/1-TCM in the same cycle
regards,
Joseph