ARM Cortex A9 writing macros for different values of cache access rates

Hi,
I am working on a project in the Zynq 7000 zc702 evaluation kit. It has an ARM Cortex A9 processor in it. I am trying to create a power model of the ARM Cortex A9 through regression analysis of the power measurements for running programs for different values of cache access rates. I was hoping if anyone could tell me how to write macros for different values of the cache access rates. Also any information on the ARM Cortex A9 would also be helpful. I am planning to use the xilinx VIVADO ISE for running the macros.