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Re: Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9?

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Hi,

 

The Cortex-A9 doesn't include any mechanism for directly reading the contents of the Level 1 cache, and assuming the Level 2 cache is the L2C-310 then this doesn't include a method to directly read the cache contents either.

 

Sorry this isn't much help, and I'm afraid I don't have any specific knowledge on the particular device you mention nor DSTREAM/DS-5, but hopefully someone else can weigh-in with some information on these.

 

Dave


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