Re: When can we expect Cortex-M7 based MCU with Dual precision FPU, because...
Hello,from the news release Atmel Unleashes Highest-Performing ARM Cortex-M7 based MCUs with Superior Memory Architecture and Connectivity for Autom… , Atmel says general sampling for the SAM E70 and...
View ArticleRe: When can we expect Cortex-M7 based MCU with Dual precision FPU, because...
Yes, that could help, although there are other concerns with ATMEL Cortex-M4/F MCUs I will not point out as the Question is about something very different - Double Precision FPU on M7. Yet these ATMEL...
View ArticleRe: Re: Inline function attribute causes undefined symbol linking error
Yes, you have accurately recreated the scenario. It is against our code standard to have a function definition in a header file. An alternate solution is to move the declaration of foo into the same...
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Re: When can we expect Cortex-M7 based MCU with Dual precision FPU, because...
Hello,you need not to close the topics because more useful comments will come from the others.Regarding Cortex-M7, it is opened that STMicro, Freescale, Atmel and Spansion have gotten the license.As...
View ArticleRe: how to set endianness in arm cortex-a8
Hi,your saying that we can't run big endian code on rvds or ds-5
View ArticleRe: how to set endianness in arm cortex-a8
On ARM-v7 there is no such thing as big endian storage of code. All memory accesses made by the instruction-side memory system are always little endian. It's nothing to do with the tool chain; the ARM...
View Articlehow to set endianness in ARM Cortex-A8
Hi,actually i need to run big endian code but i don't know how to set endian option in cp15 registers could any suggest me how to set EE bit set
View ArticleRe: Re: CMSIS DSP new functionality proposal
Hi. Unfortunately there haven't been any new functions added to the CMSIS DSP library. If it helps, here is a bit of code from our Audio Weaver tools that does an approximation to log2() and can be...
View ArticleRe: SPI in cortex-m0
You can keep HOLD high (inactive), because the data are only transferred from the slave when the master clocks the data.Make sure that you have CPOL=CPHA. If CPOL is 0, then CPHA must be 0. If CPOL is...
View ArticleCMSIS DSP new functionality proposal
CMSIS DSP is a great tool which allows Cortex-M4 devices to have a great app field range, even replacing some general purpose DSP sometimes. However I am missing some "simple" new functions that could...
View ArticleRe: Is it possible to read the raw L1/L2 cache data and tag bits on the...
Hi, The Cortex-A9 doesn't include any mechanism for directly reading the contents of the Level 1 cache, and assuming the Level 2 cache is the L2C-310 then this doesn't include a method to directly read...
View ArticleRe: Inline function attribute causes undefined symbol linking error
Stefano, Thank you for your thorough and prompt replies. You present another valid but frowned-upon method of keeping the declaration and definition of the function together by including the .c file. I...
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ARM1136 Instruction Cache Miss(EvtCount 0x0) event counts the i-cache misses...
Something weird when I count both Instruction Cache Miss event and event 0x1 (viz. Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an...
View ArticleCache Memory Requirement
Hi Experts, How to derive the cache memory requirement for the working of the software ? I could understand that each of the A/M/R processors have its own applications and build with its own Cache size...
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ARM Cortex M3 STM32F207 processor hangs during the initializing if the...
Hallo, I'm using a ARM Cortex M3 STM32F207 processor and if the code of my project becomes a value of more than 64k, the processor hangs before the PC reach the __main().The code starts at 0x08020000...
View ArticleRe: Cache Memory Requirement
How to derive the cache memory requirement for the working of the software ?Benchmarking. It's impossible to do based on theory, modern systems/cache/software is too complicated, so find a platform (or...
View ArticleRe: FVP_MPS: Write Byte Not Working for The 7-Segmenet Display?
Device control registers are typically mapped to word addresses in ARM Cortex-M products and should be accessed using the register length. On x86 byte sized control registers may be a byte apart and I...
View ArticleSystem performance analysing tool
Hi all, We have 64 bits ARM v8 and are working on system performance analysis. Share me if there are any good tools for analysis of like 1. Memory controller frequency 2. DIMM frequency 3. Socket...
View ArticleRe: FVP_MPS: Write Byte Not Working for The 7-Segmenet Display?
Hi daith, Thank you. I see.
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