Something weird when I count both Instruction Cache Miss event and event 0x1 (viz. Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an Instruction MicroTLB miss. This event occurs every cycle in which the condition is present). If I disable the branch prediction, the stall count goes up dramatically (from 177 to 643 stalls) but the cache misses do not change so much (only from 12 to 13 misses).
ps: I count the Micro TLB misses too and it always shows to be 0, so it should not be the cause of stalls.
My guess is that: the cache miss event counts only the misses in L2 cache(viz. the misses leading to a memory access), but the stalls are due to misses in L1 cache. Disabling the branch prediction might mess up the L1 cache by mis prediction but has no significant impact on L2 cache.
Anyone could help me figure out why ?
Thanks a lot.
PS: it has been confirmed from the technical manual that the event 0x0 count the L1 cache miss only. Plus a mis-predicted branch will cause event 0x1 to increment by 1. But the mismatch still exists:the stall count goes up far more than the cache miss count.
Is there anyone who could help me explain this ?