Re: ARM: 743626—An imprecise external abort, received while the processor...
Hi Stefan, Thanks for your quick response. I contacted freescale, but they suggested to contact ARM. From freescale: "Unfortunately for details it is necessary to apply to ARM (www.arm.com), actually...
View ArticleRe: How to insert DSB Instrcution to ensure that all memory accesses prior to...
To perform a data synchronization barrier operation, write CP15 with: MCR p15, 0, <Rd>, c7, c10, 4 ; Data synchronization barrier operation // From ARM reference manual.Can you please help me in...
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DS-5 debugger fails to connect to BeagleBoard-xM over JTAG
IDE: ARM DS-5 (v5.17.0)Platform: Cortex-A8 (BeagleBoard-xM)Debug agent DSTREAM (Connection Type:TCP:DSTREAM)Execution Environment...
View ArticleRe: Community French section - Section française de la communauté.
En voila un qui n'avait vraiment rien vu venir Suit tombé sur un article écrit fin 2012, d'après le rédacteur son PC a le meilleur rendement énergétique du monde.Juste pour rire des le début on sait...
View ArticleRe: Error generation on accessing Special purpose register.
Yes, I am working on AArch32.I have used the 32Arch equivalent using this code:asm("ldr r0, =0x00");asm("MCR ICC_SEIEN, r0") ; And now I am getting this error: Error: bad or missing co-processor number...
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Re: DS-5 debugger fails to connect to BeagleBoard-xM over JTAG
Thanks everyone, It's due to wrong selection of Target Interface Connections "ARM jtag 20 "right one is TI jtag 20
View ArticleRe: How to insert DSB Instrcution to ensure that all memory accesses prior to...
Hi, To answer further, I need to know which ARM processor you are using and also which device. Can you supply that information? Chris
View ArticleRe: Error generation on accessing Special purpose register.
Actually, I think MCR is not the right instruction. You should use MSR to copy a general purpose register to a special purpose register. I think it should then work. Chris
View ArticleRe: ARM: 743626—An imprecise external abort, received while the processor...
Hi, I have seen your exchange with Freescale on their community site. They are correct to refer you to ARM since this erratum refers to the Cortex-A9 processor core and not to any other component of...
View ArticleRe: Is there are way to add sub-navigation to a document?
If what you want is like in How to Join the ARM Connected Community Partner Program (For Company Space):- add proper Heading style to your section titles. (See Style Guide - Content Creation: Font,...
View ArticleVMLS slower than two separate instructions?
Hi All, Iv'e been playing with NEON (gcc intrinsics on A15 core) for a few weeks and I've come across something which does make much sense, and was hoping that someone might be able to shed some light...
View ArticleRe: VMLS slower than two separate instructions?
Hi again, I took a peek at what gcc was doing, it is adding in vorr's in what I assume is an attempt to manage the pipeline (yippie): 0x00008548 <+24>: vmul.i32 d16, d16, d18...
View ArticleRe: How to insert DSB Instrcution to ensure that all memory accesses prior to...
Hi,Im using Cortex-A9 processor Manyam
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Re: How to configure a 10 inch TFT LCD in ARM Cortex-M3?
I've found a display, which supports 1024x600; it's not the same display, but it might be compatible, regarding sync lengths and signals.
View ArticleWhat's the function or effect of Address[63:55] bits in ARMv8?
Hello, I'm studying ARMv8 memory. ARMv8 AArch64 supports max 48 bits VA, if TBIn is 1, EL1&0 address [63:55] are forced to sign extension of bit[55]. Is the only use of [63:55] to decide...
View Articlearmv8 hypervisor switching between two OS
Hello, I need to run two OS, Linux with 64-bit and RTOS with 32-bit, in the Cortex A53 which is armv8 architecture. It is not clear to me while reading the ARMv8 reference manual as how can we use EL2...
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Fast Model Profiling
Hi I'm interesting in profiling with ARM fast model. As I understand, fast model doesn't suport cycle accurate profile.So I'd like to estimate with fast model profile information. 1. How accurate...
View ArticleRe: armv8 hypervisor switching between two OS
So first I want to know if its possible to run two OS having different execution state on the same exception level? If yes how does the hypersior code running on EL2 switch between them? Short answer...
View ArticleWhere do I find libraries and sample code ?
I just bought a couple of Freescale MCUs, including the MKE04Z8 family.I've been to freescale.com and searched for sample code and libraries, but couldn't find anything.Where do I download the...
View ArticleRe: Fast Model Profiling
if you enabled cache model in fast model, you can see cache load/hit/miss number, you can use it for evaluation, but timing info is not accurate.
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