Re: Please explain to Grandma: What’s the SAM D20 Xplained Dev Board?
Be sure to include a debate on the difference between GPL2 and GPL3 and whether or not the Apache licence followers are traitors or enlightened and pragramatic.
View ArticleHow to Access Physical Counter in ARM Cortex-A7?
Hello, I have an custom FPGA board running ARM Cortex-A7 processor. I want to access the system physical counter. According to the ARM architecture reference manual I am trying to access the...
View ArticleRe: After boot from ROM, I need to execute code in another memory. How can I...
There's a bit about debugging hardfault at Debugging a Cortex-M0 Hard Fault Are you sure the code has been loaded into the target location? A simple boot startup may only have set up the data and zero...
View ArticleRe: Where / to whom should I report a suspected bug in the Cortex-M CMSIS...
Hello Try cmsis@arm.comIf that doesn't work - email me: bob.boys@arm.com Thanks for the feedback Bob
View ArticleRe: How to load Linux kernel image onto ARM Cortex-A9 target using DSTREAM...
Hello MWSealey,Thank you very much for your reply. I tried the zImage approach you suggested using restore command and got it working.
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Where / to whom should I report a suspected bug in the Cortex-M CMSIS headers?
I apologize if this is not strictly on-topic, but I couldn't find an appropriate forum here for CMSIS-related questions, and the ARM top-level web site doesn't have any obvious place to report bugs. I...
View ArticleRe: Typical L1 and L2 access latency for SoCs made of ARM Cortex-A9
CA9 TRM has said something.
View ArticleRe: Community French section - Section française de la communauté.
Il est peut-etre meilleur rédacteur que technicien
View ArticleRe: After boot from ROM, I need to execute code in another memory. How can I...
Hi Daith, It was a basic issue. I Didn't know that the BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0. I should have given ((void (*) (void)) 0x21000001) (); Thanks,Shyam
View ArticleRe: is there any tool to transfer hex number to corresponding arm assembler...
I don't know of a tool that specifically does this. In the past when I've had to do this I use one of two (similar) approaches. (1)* Open a debugger (such as DS-5 or RVD) and connect to a target...
View ArticleRe: Typical L1 and L2 access latency for SoCs made of ARM Cortex-A9
Hi, I'm afraid this is a question which does not have an easy or definitive answer! Because of the unique way in which ARM-based SoCs are put together, all behave slightly differently. The latency of...
View ArticleHow to find serial number for generating trial license
Hi Experts, How to find the serial number of the installed DS-5 evaluation product ? It is required to generate the evaluation license for the DS-5 products.
View ArticleRe: Cortex-A8 : instruction fetch for dual-issue
Hi, Thanks for your question. I suspect that your model is a little too simplistic. If you look at Chapter 16 of the Cortex-A8 Technical Reference Manual, you will see that there are restrictions on...
View ArticleRe: How to find serial number for generating trial license
Have you followed the sequence of steps on this page? http://ds.arm.com/developer-resources/tutorials/working-with-arm-ds-5/ You don't need a serial number - you just need to select the "Generate a 30...
View ArticleRe: After boot from ROM, I need to execute code in another memory. How can I...
Oh yes sorry about that, that was really silly of me, I should have spotted that especially as I've had to do something very similar myself in the past.
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Re: 如何理解read-allocate / write-allocate in AXI4 spec
Hi chinatiger, >AXI4 Memory attributes有: Read-Allocate / Write-Allocate. AXI4中，对AxCACHE信号的定义作出了更新： AWCACHE[3]： AllocateAWCACHE[2]: Other AllocateARCACHE[3]: Other AllocateARCACHE[2]: Allocate 详细介绍请看...
View ArticleRe: Cache lock down in ARM CortexA7
Hi Peter, Thanks a lot for your detailed description. Could you please explain following line little better : It is also worth noting that in many markets needing realtime response, TCM is generally...
View ArticleRe: Re: Cache lock down in ARM CortexA7
Hi Anshul, Could you please explain following line little better : It is also worth noting that in many markets needing realtime response, TCM is generally available as a synthesis option in the...
View ArticleRe: Re: Cache lock down in ARM CortexA7
Hi Peter, Thanks a lot for clarification. I want to try it on some other hardware. If possible please guide me how to perform cache lock down on some piece of code. I want to check the impact of cache...
View ArticleRe: Cache lock down in ARM CortexA7
It depends a little on the hardware you have, so I would check the TRM. For example – here are the instructions for the L220 cache controller:...
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